
_start:

	TLBI ALLE3
	// msr CPTR_EL3, xzr
	// mrs x1, mair_el3

create_simple_page_table:	

	// config page table, base addr 0x8c000000
	ldr x2, =0x8c000000
	msr TTBR0_EL3, x2

	// level 0
	ldr x3, =0x8d000003
	str x3, [x2]

	// level 1
	ldr x3, =0x8e000003
	ldr x2, =0x8d000010
	str x3, [x2]
	ldr x2, =0x8d000008
	str x3, [x2]
	ldr x2, =0x8d000000
	str x3, [x2]

	// level 2
	ldr x2, =0x8e000000
	ldr x3, =0x8f000003
	str x3, [x2]

	// level 3
	ldr x2, =0x8f000000
	// [10]: af bit set 1
	ldr x3, =0x80000403
	str x3, [x2]
	isb
	DSB sy

enable_mmu:
	// ia 48, oa 48, page 4kb
	ldr x1, =0x81858010
	msr TCR_EL3, x1

	mrs x2, SCTLR_EL3
	mov x3, 0x1
	bfi x2, x3, #0, 1
	// // cache
	// bfi x2, x3, #2, 1
	msr SCTLR_EL3, x2
	isb
	
loop:
	ldr x3, [x1]
	b loop
